Draft:Robert K. Montoye

Robert K. (Bob) Montoye is a senior computer scientist at the IBM T. J. Watson Research Center in Yorktown Heights, New York.

Biography[edit]

Montoye's area of expertise is computer architecture, hardware and semiconductor chip design. He is one of the original designers of IBM POWER Architecture^[1].

In 2014, along with fellow IBM researchers Jing Li, Masatoshi Ishii and Leland Chang, he demonstrated a design of Ternary content-addressable memory (TCAM) using 2-transistor/2-resistive-storage that has more than ten times smaller cell size than SRAM based TCAM at the same technology node.^[2]

References[edit]

^ Bakoglu, H. B.; Grohoski, G. F.; Montoye, R. K. (January 1990). "The IBM RISC System/6000 processor: Hardware overview". IBM Journal of Research and Development. 34 (1): 12–22. doi:10.1147/rd.341.0012.
^ Jing Li, Robert Montoye, Masatoshi Ishii and Leland Chang: 1 Mb 0.41 μm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing, IEEE J. Solid State Circuits, 2014.

External links[edit]

Drafts moved from mainspace

[1] Bakoglu, H. B.; Grohoski, G. F.; Montoye, R. K. (January 1990). "The IBM RISC System/6000 processor: Hardware overview". IBM Journal of Research and Development. 34 (1): 12–22. doi:10.1147/rd.341.0012.

[2] Jing Li, Robert Montoye, Masatoshi Ishii and Leland Chang: 1 Mb 0.41 μm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing, IEEE J. Solid State Circuits, 2014.

[1]

[2]